Impact of Chip-Package Interaction in Microelectronics

The exponential growth in integrated device density has yielded high-performance microprocessors containing almost 1 billion transistors per chip for the current 65 nm technology, up to now it is maybe 45nm technology. Continuous scaling of the devices and performance requires innovations in materials, processes, and designs for both back-end-of-line (BEoL) interconnects and packaging structures. Mechanical reliability has been a limiting factor for implementation of new materials and processes[1]. Electronic assemblies are the heart of all modern electronics. They house the essential chip, generate semiconductor input/output, and take care of the heat generated by the process. The explosive growth of communications and consumer electronics applications has suddenly made a knowledge of the fabrication process a very in-demand and lucrative skill. Even beginners, with no advanced degrees or mathematical backgrounds will be able to quickly and easily learn the entire electronic assembly fabrication process with this well-illustrated comprehensive tutorial[2].
It does not need to emphasize how important it is for our world, especially for academics to go out of papers and books. In the area of the mechanics of interconnects, Zhigang Suo recommanded two particular works in his blog. If you want to get into this research field, studying them might give a perspective. There two works are listed as following[1]:
R.H. Dauskardt, M. Lane, Q. Ma and N. Krishna, Adhesion and debonding of multilayer thin film structures. Engineering Fracture Mechanics 61, 141-162 (1998). This paper developed the 4-point bending method. Although the mechanics and the technique themselves were already known at the time, the collaboration between Reiner Dauskardt, of Standford, and Qing Ma, of Intel, really reduced the interfacial fracture mechanics to industrial practice. Their method is now widely adopted in the industry. This work has markedly enhanced the appreciation of fracture mechanics in the microelectronic industry.
M.A. Korhonen, P. Borgesen, K.N. Tu, and C.Y. Li, Stress evolution due to electromigration in confined metal lines. J. Appl. Phys. 73, 3790 (1993). This is a work resulting from a collaboration between Cornnel and IBM. Again, much of the basic ingredients was known when this paper was published. But the authors put the ingredients together, and clearly linked electromigration to the mechanical behavior of the interconnect structure. This paper has become the foundation of subsequent analysis of electromigration.
Both of these works remain important as we study low-k interconnect structures. Resouces to learn about challenges in the semiconductor industry:
International Technology Roadmap for Semiconductors. On this site you can download the famous Roadmaps, the industrial consensus of how to reach the moving target. The target, of course, has been to make Moore's law real. The Roadmaps spell out future needs of the industry, which drive today's research and development.
JEDEC. The developer of standards for the solid-state industry. All publications are free online. For example, JEP112 is entitled "Failure Mechanisms and Models for Silicon Devices".
to be continued
[1] http://www.imechanica.org/node/2880
[2] Electronic Assembly Fabrication : Chips, Circuit Boards, Packages, and Components

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1 comments:

  1. Dr. Yongan Huang Says:

    In this paper, an overview of the development of prediction study on the thermal fatigue life of electronic packages is presented, including theore-tical and experimental aspects as well as failure mechanism analysis. A pro-phecy on the research trend in this area is suggested.
    论文信息:贺思军 孙学伟. 封装结构的热疲劳寿命预估研究进展. 力学进展 ;1996  26 (1): 107-113